Filed under: engineering | tstotts dot net Weblog

ezra red trac

timotheus — 2009-11-10T01:43:56-05:00

To further expedite my efforts at developing Ezra Red — my HDL revising and rewriting application — I have created a Trac wiki and ticket site for the project. The Ezra Red Trac site permits anonymous viewing of all project progress and tickets. Actual source-code viewing is not permitted though as this application is closed-source.

ezra red application

timotheus — 2009-10-15T00:33:18-05:00

“Ezra Red” is the code name for the new HDL revising and rewriting application that I am developing as a personal project. After several weeks of studying the Netbeans platform, I have begun a branch of my original HDL rewriting application that will utilize the Netbeans RCP instead of a custom command-line interface and a custom Swing GUI. Using the Netbeans Platform as a basis for my application will allow me to focus more on discipline specific coding, such as the language parsing and tree rewriting of an HDL project; and not spend so much time concerning myself with the presentation and usability of the application. To track what functionality needs to be implemented, I have created a Task List.

netbeans study-up

timotheus — 2009-09-22T23:34:17-05:00

After some futher consideration, I have elected to try creating a branch of my HDL rewriting tool as a combination of the Antlr v3 and Netbeans projects, instead of Antlr with a custom user interface. Rather than reinvent what another project freely provides, I hope to make a relatively adroit user experience by utilizing the Netbeans Platform APIs. Watching the API screencasts, Netbeans could be just what I am looking for.

hdl model rewriting tool

timotheus — 2009-09-15T20:22:29-05:00

To keep myself occupied while job searching, I have created the initial workings of a software tool to rewrite HDL source files according to a set of user-specified rules. The tool employs the open source ANTLR v3 project to implement a full VHDL-2008 lexer and parser. (Verilog might also be added.) The open source ANTLR technology supports building token rewritable Abstract Syntax Trees; and I have created IEEE 1076-2008 compliant grammar files that make full use of this feature. The grammars are complete, unsimplified, and modestly optimized for LL(*) parsing speed.

For the time being I have chosen not to release many details, including potential use cases, or even what I hope the tool to have as an eventual product name (trademarked?). However, the basic functionality of the software is simple: input HDL models, analyze, rewrite according to a set of high-level user-provided rules, output new valid and verified HDL models. As of now, the lexer, parser, and XML "project file" file format are implemented and working, along with automated high-level regression test cases; and a graphical user interface is under development. My first milestone of functionality completed is the ability to—what I will term "hardcode" or "partially-compile"—fully evaluate constant declarations within a VHDL project, within the VHDL context of package, architecture, or entity, and then remove the declaration(s) from the sources.

After some extensive research, the most cost-effective route for implementing a proprietary HDL rewriting tool, based on compiler theory (and not just scripting some regular expressions), with lowest-cost technology turned out to be Java. The Java language has a good selection of mature compiler-compilers available for the creation of lexers and parsers. This particular language will also allow the tool to operate on nearly any desktop, and not just the Windows operating system. Since the tool is not intended as a source code editor, but rather a batch operation processor, a custom Swing GUI was decided to be sufficient. Had I intended the tool to be a source code editor I probably would have followed the path of other developers in creating an extension of the Eclipse or Netbeans projects. My modest, yet pragmatic GUI will allow the user to create an XML project file that specifies a list of batch operations and their respective parameters.

vhdl modular design

timotheus — 2009-04-28T01:18:25-05:00

With his text, VHDL: Modular Design and Synthesis of Cores and Systems, professor Z. Navabi of Northeastern University dives into VHDL as a modern software modeling tool for ASIC and FPLD designs. He provides a quick overview of implementing VHDL designs, testbenches, and configurations; and then continues to build upon this foundation with an in-depth treatment of the VHDL language. The book concludes with designing testable cores and the full development of a processor core.

Following his text and implementing each of the chapter problems, I have noticed a few areas of his language treatment that were ignored both in my classroom studies as well as my industry experience. One such language feature is the VHDL block with guarded signal assignment.

The VHDL block is essentially the concurrent analogy to the sequential process. Both may be used to create latches and flip-flops. As an example, the following shows a D flip-flop in both concurrent (block) and sequential (process) forms.

-- Concurrent D flip-flop with rising edge sensitivity.
dff_concur: BLOCK (clk = '1' AND NOT clk'STABLE)
BEGIN
  q <= GUARDED d;
END BLOCK dff_concur;

-- Sequential D flip-flop with rising edge sensitivity.
dff_sequent: PROCESS (clk)
BEGIN
  IF (clk = '1' and clk'EVENT) THEN
    q <= d;
  END IF;
END PROCESS dff_sequent;

I cannot help but wonder if synthesis tools treat the concurrent block form any differently.