vhdl modular design

With his text, VHDL: Modular Design and Synthesis of Cores and Systems, professor Z. Navabi of Northeastern University dives into VHDL as a modern software modeling tool for ASIC and FPLD designs. He provides a quick overview of implementing VHDL designs, testbenches, and configurations; and then continues to build upon this foundation with an in-depth treatment of the VHDL language. The book concludes with designing testable cores and the full development of a processor core.

Following his text and implementing each of the chapter problems, I have noticed a few areas of his language treatment that were ignored both in my classroom studies as well as my industry experience. One such language feature is the VHDL block with guarded signal assignment.

The VHDL block is essentially the concurrent analogy to the sequential process. Both may be used to create latches and flip-flops. As an example, the following shows a D flip-flop in both concurrent (block) and sequential (process) forms.

-- Concurrent D flip-flop with rising edge sensitivity.
dff_concur: BLOCK (clk = '1' AND NOT clk'STABLE)
BEGIN
  q <= GUARDED d;
END BLOCK dff_concur;

-- Sequential D flip-flop with rising edge sensitivity.
dff_sequent: PROCESS (clk)
BEGIN
  IF (clk = '1' and clk'EVENT) THEN
    q <= d;
  END IF;
END PROCESS dff_sequent;

I cannot help but wonder if synthesis tools treat the concurrent block form any differently.